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Dual Channel Isolators with Integrated DC-to-DC Converter ADuM5200/ADuM5201/ADuM5202
FEATURES
isoPower integrated isolated dc-to-dc converter Regulated 3 V or 5 V output Up to 500 mW output power Dual dc-to-25 Mbps (NRZ) signal isolation channels Schmitt trigger inputs 16-lead SOIC package with >8 mm creepage High temperature operation: 105C maximum High common-mode transient immunity: >25 kV/s Safety and regulatory approvals UL recognition 2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A (pending) VDE certificate of conformity (pending) DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 560 V peak
FUNCTIONAL BLOCK DIAGRAM
VDD1 1 GND1 2 VIA/VOA 3 2-CHANNEL iCOUPLER CORE VIB/VOB 4 RCIN 5 RCSEL 6 VE1/NC 7 GND1 8
13 12 11 10 9
OSC
RECT
REG
16 15 14
VISO GNDISO VIA/VOA VIB/VOB NC VSEL VE2/NC GNDISO
07540-001
ADuM5200/ ADuM5201/ ADuM5202
Figure 1.
VIA
3 14
VOA
APPLICATIONS
RS-232/RS-422/RS-485 transceivers Industrial field bus isolation Power supply startups and gate drives Isolated sensor interfaces Industrial PLCs
VIA
4
13
Figure 2. ADuM5200
3 14
VOA
4
13
Figure 3. ADuM5201
VOA
3 14
VIA
4
13
Figure 4. ADuM5202
GENERAL DESCRIPTION
The ADuM520x1 are dual channel digital isolators with isoPower, an integrated, isolated dc-to-dc converter. Based on the Analog Devices, Inc., iCoupler(R) technology, the dc-to-dc converter provides up to 500 mW of regulated, isolated power with 5.0 V input and 5.0 V output voltage, or 200 mW of power with 3.3 V input and 3.3 V output voltage. This eliminates the need for a separate isolated dc-to-dc converter in low power isolated designs. The Analog Devices chip scale transformer iCoupler technology is used for the isolation of the logic signals as well as for the dc-to-dc converter. The result is a small form factor, total isolation solution. ADuM520x units can be used in combination with the ADuM5401, ADuM5402, ADuM5403, ADuM5404, and ADuM5000 with isoPower(R) to achieve higher output power
1
levels and greater channel counts (see the Increasing Available Power section). The ADuM520x isolators provide two independent isolation channels in a variety of channel configurations and data rates (see the Ordering Guide for options). isoPower uses high frequency switching elements to transfer power through its transformer. Special care must be taken during printed circuit board (PCB) layout to meet emissions standards. Refer to the AN-0971 application note for details on board layout recommendations.
Protected by U.S. Patents: 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
07540-004
VOB
ADuM5202
VIB
07540-003
VOB
ADuM5201
VIB
07540-002
VIB
ADuM5200
VOB
ADuM5200/ADuM5201/ADuM5202 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Electrical Characteristics--5 V Primary Input Supply/5 V Secondary Isolated Supply .......................................................... 3 Electrical Characteristics--3.3 V Primary Input Supply/3.3 V Secondary Isolated Supply .......................................................... 5 Package Characteristics ............................................................... 7 Regulatory Information ............................................................... 7 Insulation and Safety-Related Specifications ............................ 7 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics .............................................................................. 8 Recommended Operating Conditions ...................................... 9 Absolute Maximum Ratings.......................................................... 10 ESD Caution ................................................................................ 10 Pin Configurations and Function Descriptions ......................... 11 Typical Performance Characteristics ........................................... 15 Terminology .................................................................................... 17 Applications Information .............................................................. 18 PCB Layout ................................................................................. 18 EMI Considerations ................................................................... 18 Propagation Delay Parameters ................................................. 19 DC Correctness and Magnetic Field Immunity........................... 19 Power Consumption .................................................................. 20 Current Limit and Thermal Overload Protection ................. 20 Power Considerations ................................................................ 21 Thermal Analysis ....................................................................... 21 Increasing Available Power ....................................................... 21 Insulation Lifetime ..................................................................... 22 Outline Dimensions ....................................................................... 23 Ordering Guide .......................................................................... 23
REVISION HISTORY
10/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 24
ADuM5200/ADuM5201/ADuM5202 SPECIFICATIONS
ELECTRICAL CHARACTERISTICS--5 V PRIMARY INPUT SUPPLY/5 V SECONDARY ISOLATED SUPPLY
4.5 V VDD1 5.5 V, VSEL = VISO; each voltage is relative to its respective ground. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25C, VDD = 5.0 V, VISO = 5.0 V, VSEL = VISO. Table 1.
Parameter DC-TO-DC CONVERTER POWER SUPPLY Setpoint Line Regulation Load Regulation Output Ripple Output Noise Switching Frequency Pulse-Width Modulation Frequency DC-to-2 Mbps Data Rate1 Maximum Output Supply Current 2 Efficiency @ Maximum Output Supply Current 3 IDD1 Supply Current, No VISO Load 25 Mbps Data Rate (CRWZ Grade Only) IDD1 Supply Current, No VISO Load ADuM5200 ADuM5201 ADuM5202 Available VISO Supply Current 4 ADuM5200 ADuM5201 ADuM5202 IDD1 Supply Current, Full VISO Load5 Undervoltage Lockout, VDD1 and VISO Supply 6 Positive Going Threshold Negative Going Threshold Hysteresis iCoupler DATA CHANNELS I/O Input Currents Logic High Input Threshold Logic Low Input Threshold Symbol VISO VISO(LINE) VISO(LOAD) VISO(RIP) VISO(N) fOSC fPWM IISO(MAX) 100 34 IDD1(Q) 8 22 Min 4.7 Typ 5.0 1 1 75 200 180 625 Max 5.4 5 Unit V mV/V % mV p-p mV p-p MHz kHz mA % mA Test Conditions IISO = 0 mA IISO = 50 mA, VDD1 = 4.5 V to 5.5 V IISO = 10 mA to 90 mA 20 MHz bandwidth, CBO = 0.1 F||10 F, IISO = 90 mA CBO = 0.1 F||10 F, IISO = 90 mA
VISO > 4.5 V, dc to 1 MHz logic signal frequency IISO = 100 mA, dc to 1 MHz logic signal frequency IISO = 0 mA, dc to 1 MHz logic signal frequency
IDD1(D) IDD1(D) IDD1(D)
34 38 41
mA mA mA
IISO = 0 mA, CL = 15 pF, 12.5 MHz logic signal frequency IISO = 0 mA, CL = 15 pF, 12.5 MHz logic signal frequency IISO = 0 mA, CL = 15 pF, 12.5 MHz logic signal frequency CL = 15 pF, 12.5 MHz logic signal frequency CL = 15 pF, 12.5 MHz logic signal frequency CL = 15 pF, 12.5 MHz logic signal frequency CL = 0 pF, dc to 1 MHz logic signal frequency, VDD = 4.5 V, IISO = 100 mA
IISO(LOAD) IISO(LOAD) IISO(LOAD) IDD1(MAX)
94 92 90 290
mA mA mA mA
VUV+ VUV- VUVH IIA, IIB VIH VIL -20 0.7 x VISO, 0.7 x VIDD1
2.7 2.4 0.3 +0.01 +20
V V V A V V
0.3 x VISO, 0.3 x VIDD1
Rev. 0 | Page 3 of 24
ADuM5200/ADuM5201/ADuM5202
Parameter Logic High Output Voltages Symbol VOAH, VOBH VOAH, VOBH Logic Low Output Voltages AC SPECIFICATIONS ADuM520xARWZ 7 Minimum Pulse Width Maximum Data Rate Propagation Delay Pulse Width Distortion, |tPLH - tPHL| Propagation Delay Skew Channel-to-Channel Matching ADuM520xCRWZ Minimum Pulse Width7 Maximum Data Rate Propagation Delay Pulse Width Distortion, |tPLH - tPHL| Change vs. Temperature Propagation Delay Skew Channel-to-Channel Matching, Codirectional Channels Channel-to-Channel Matching, Opposing-Directional Channels For All Models Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output Common-Mode Transient Immunity at Logic Low Output Refresh Rate
1 2
Min VDD1 - 0.3, VISO - 0.3 VDD1 - 0.5, VISO - 0.5
Typ 5.0 4.8 0.0 0.0
Max
Unit V V
Test Conditions IOx = -20 A, VIx = VIxH IOx = -4 mA, VIx = VIxH IOx = 20 A, VIx = VIxL IOx = 4 mA, VIx = VIxL
VOAL, VOBL
0.1 0.4
V V
PW 1 tPHL, tPLH PWD tPSK tPSKCD, tPSKOD PW 25 tPHL, tPLH PWD tPSK tPSKCD tPSKOD 45 5 55
1000 100 40 50 50 40 60 6 15 6 15
ns Mbps ns ns ns ns ns Mbps ns ns ps/C ns ns ns
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
tR/tF |CMH| |CML| fr
25 25
2.5 35 35 1.0
ns kV/s kV/s Mbps
CL = 15 pF, CMOS signal levels VIx = VDD or VISO, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, V = 1000 V, transient magnitude = 800 V
The contributions of supply current values for all four channels are combined at identical data rates. VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps, data I/O channels draw additional current proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. The dynamic I/O channel load must be treated as an external load and be included in the VISO power budget. 3 The power demands of the quiescent operation of the data channels cannot be separated from the power supply section. Efficiency includes the quiescent power consumed by the I/O channels as part of its internal power consumption. 4 This current is available for driving external loads at the VISO pin. All channels are simultaneously driven at a maximum data rate of 25 Mbps with the full capacitive load representing the maximum dynamic load conditions. Refer to the Power Consumption section for the calculation of available current at less than the maximum data rate. 5 IDD1(MAX) is the input current under full dynamic and VISO load conditions. 6 Undervoltage lockout (UVLO) holds the outputs in a low state if the corresponding input or output power supply is below the referenced threshold. Hysteresis is built into the detection threshold to prevent oscillations and noise sensitivity. 7 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
Rev. 0 | Page 4 of 24
ADuM5200/ADuM5201/ADuM5202
ELECTRICAL CHARACTERISTICS--3.3 V PRIMARY INPUT SUPPLY/3.3 V SECONDARY ISOLATED SUPPLY
3.0 V VDD1 3.6 V, VSEL = GNDISO; each voltage is relative to its respective ground. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TA = 25C, VDD = 3.3 V, VISO = 3.3 V, VSEL= GNDISO. Table 2.
Parameter DC-TO-DC CONVERTER POWER SUPPLY Setpoint Line Regulation Load Regulation Output Ripple Output Noise Switching Frequency Pulse-Width Modulation Frequency DC to 2 Mbps Data Rate1 Maximum Output Supply Current 2 Efficiency @ Maximum Output Supply Current 3 IDD1 Supply Current, No VISO load IDD1 Supply Current, Full VISO load 25 Mbps Data Rate (CRWZ Grade Only) IDD1 Supply Current, No VISO Load4 ADuM5200 ADuM5201 ADuM5202 Available VISO Supply Current 5 ADuM5200 ADuM5201 ADuM5202
Undervoltage Lockout (UVLO), VDD1 and VISO Supply 6 Positive Going Threshold Negative Going Threshold Hysteresis
Symbol VISO VISO(LINE) VISO(LOAD) VISO(RIP) VISO(N) fOSC fPWM IISO(MAX)
Min 3.13
Typ 3.3 1 1 50 130 180 625
Max 3.37 5
Unit V mV/V % mV p-p mV p-p MHz kHz mA
Test Conditions IISO = 0 mA IISO = 30 mA, VDD1 = 3.0 V to 3.6 V IISO = 6 mA to 54 mA 20 MHz bandwidth, CBO = 0.1 F||10F, IISO = 54 mA CBO = 0.1F||10F, IISO = 54 mA
60 36
% 15 mA mA
IDD1(Q) IDD1(MAX)
6 175
VISO > 3.0 V, dc to 1 MHz logic signal frequency IISO = 60 mA, dc to 1 MHz logic signal frequency IISO = 0 mA, dc to 1 MHz logic signal frequency
CL = 0 pF, f = 0 MHz, VDD = 3.3 V, IISO = 60 mA
IDD1(D) IDD1(D) IDD1(D)
23 25 27
mA mA mA
IISO = 0 mA, CL = 15 pF, 12.5 MHz logic signal frequency IISO = 0 mA, CL = 15 pF, 12.5 MHz logic signal frequency IISO = 0 mA, CL = 15 pF, 12.5 MHz logic signal frequency CL = 15 pF, 12.5 MHz logic signal frequency CL = 15 pF, 12.5 MHz logic signal frequency CL = 15 pF, 12.5 MHz logic signal frequency
IISO(LOAD) IISO(LOAD) IISO(LOAD)
56 55 54
mA mA mA
VUV+ VUV- VUVH
2.7 2.4 0.3
V V V
iCoupler DATA CHANNELS I/O Input Currents Logic High Input Threshold Logic Low Input Threshold Logic High Output Voltages
IIA, IIB VIH VIL VOAH, VOBH VOAH, VOBH VOAL, VOBL VOAL, VOBL
-20
0.7 x VISO, 0.7 x VIDD1
+0.01
+20
A V V V V IOx = -20 A, VIx = VIxH IOx = -4 mA, VIx = VIxH IOx = 20 A, VIx = VIxL IOx = 4 mA, VIx = VIxL
0.3 x VISO, 0.3 x VIDD1 VDD1 - 0.2, VISO - 0.2 VDD1 - 0.5, V1SO - 0.5
3.3 3.1 0.0 0.0 0.1 0.4
Logic Low Output Voltages
V V
Rev. 0 | Page 5 of 24
ADuM5200/ADuM5201/ADuM5202
Parameter AC SPECIFICATIONS ADuM520xARWZ Minimum Pulse Width 7 Maximum Data Rate Propagation Delay Pulse Width Distortion, |tPLH - tPHL| Propagation Delay Skew Channel-to-Channel Matching ADuM520xCRWZ Minimum Pulse Width7 Maximum Data Rate Propagation Delay Pulse Width Distortion, |tPLH - tPHL| Change vs. Temperature Propagation Delay Skew Channel-to-Channel Matching, Codirectional Channels Channel-to-Channel Matching, Opposing-Directional Channels For All Models Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic High Output Common-Mode Transient Immunity at Logic Low Output Refresh Rate
1 2
Symbol
Min
Typ
Max
Unit
Test Conditions
PW 1 tPHL, tPLH PWD tPSK tPSKCD, tPSKOD PW 25 tPHL, tPLH PWD tPSK tPSKCD tPSKOD 45 5 60
1000 100 40 50 50 40 60 6 45 6 15
ns Mbps ns ns ns ns ns Mbps ns ns ps/C ns ns ns
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
tR/tF |CMH| |CML| fr
25 25
2.5 35 35 1.0
ns kV/s kV/s Mbps
CL = 15 pF, CMOS signal levels VIx = VDD or VISO, VCM = 1000 V, transient magnitude = 800 V VIx = 0 V, V = 1000 V, transient magnitude = 800 V
The contributions of supply current values for all four channels are combined at identical data rates. VISO supply current is available for external use when all data rates are below 2 Mbps. At data rates above 2 Mbps data I/O channels draw additional current proportional to the data rate. Additional supply current associated with an individual channel operating at a given data rate may be calculated as described in the Power Consumption section. The dynamic I/O channel load must be treated as an external load and be included in the VISO power budget. 3 The power demands of the quiescent operation of the data channels cannot be separated from the power supply section. Efficiency includes the quiescent power consumed by the I/O channels as part of its internal power consumption. 4 IDD1(D) is the typical input supply current with all channels simultaneously driven at a maximum data rate of 25 Mbps with the full capacitive load representing the maximum dynamic load conditions. Treat resistive loads on the outputs separately from the dynamic load. 5 This current is available for driving external loads at the VISO pin. All channels are simultaneously driven at a maximum data rate of 25 Mbps with the full capacitive load representing the maximum dynamic load conditions. Refer to the Power Consumption section for the calculation of available current at less than the maximum data rate. 6 Undervoltage lockout (UVLO) holds the outputs in a low state if the corresponding input or output power supply is below the referenced threshold. Hysteresis is built into the detection threshold to prevent oscillations and noise sensitivity. 7 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
Rev. 0 | Page 6 of 24
ADuM5200/ADuM5201/ADuM5202
PACKAGE CHARACTERISTICS
Table 3.
Parameter RESISTANCE AND CAPACITANCE Resistance (Input-to-Output) 1 Capacitance (Input-to-Output)1 Input Capacitance 2 IC Junction to Ambient Thermal Resistance Symbol RI-O CI-O CI JA Min Typ 1012 2.2 4.0 45 Max Unit pF pF C/W Test Conditions
f = 1 MHz Thermocouple located at the center of the package underside; test conducted on a 4-layer board with thin traces 3 TJ rising
THERMAL SHUTDOWN Threshold Hysteresis
1 2
TSSD TSSD-HYS
150 20
C C
This device is considered a 2-terminal device; Pin 1 through Pin 8 are shorted together, and Pin 9 through Pin 16 are shorted together. Input capacitance is from any input data pin to ground. 3 Refer to the Power Considerations section for thermal model definitions.
REGULATORY INFORMATION
The ADuM5200/ADuM5201/ADuM5202 are approved by the organizations listed in Table 4. Refer to Table 9 and the Insulation Lifetime section for details regarding recommended maximum working voltages for specific cross isolation waveforms and insulation levels. Table 4.
UL Recognized under 1577 Component Recognition Program 1 Single Protection 2500 V RMS Isolation Voltage File E214100
1 2
CSA (Pending) Approved under CSA Component Acceptance Notice #5A Reinforced insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (566 V peak) maximum working voltage File 205078
VDE (Pending) Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 2 Reinforced insulation, 560 V peak
File 2471900-4880-0001
In accordance with UL 1577, each ADuM520x is proof tested by applying an insulation test voltage 3000 V rms for 1 sec (current leakage detection limit = 5 A). In accordance with DIN V VDE V 0884-10, each ADuM520x is proof tested by applying an insulation test voltage 1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Table 5.
Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Minimum External Tracking (Creepage) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group Symbol Value 2500 L(I01) >8 min L(I02) Unit Conditions V rms 1-minute duration mm Measured from input terminals to output terminals, shortest distance through air >8 min mm Measured from input terminals to output terminals, shortest distance path along body 0.017 min mm Distance through the insulation >175 V DIN IEC 112/VDE 0303 Part 1 IIIa Material group (DIN VDE 0110, 1/89, Table 1)
CTI
Rev. 0 | Page 7 of 24
ADuM5200/ADuM5201/ADuM5202
DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS
These isolators are suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. The * marking on packages denotes DIN V VDE V 0884-10 approval. Table 6.
Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage 150 V rms For Rated Mains Voltage 300 V rms For Rated Mains Voltage 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage Method b1 Method a After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Safety-Limiting Values Case Temperature Side 1 IDD1 Current Insulation Resistance at TS Conditions Symbol Characteristic I to IV I to III I to II 40/105/21 2 560 1050 Unit
VIORM VIORM x 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC VIORM x 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VIORM x 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC Transient overvoltage, tTR = 10 sec Maximum value allowed in the event of a failure (see Figure 5) VTR VPR VPR
V peak V peak
896 672 4000
V peak V peak V peak
VIO = 500 V
TS IS1 RS
150 555 >109
C mA
Thermal Derating Curve
600
SAFE OPERATING VDD1 CURRENT (mA)
500
400
300
200
100
0
50 100 150 AMBIENT TEMPERATURE (C)
200
Figure 5. Thermal Derating Curve, Dependence of Safety Limiting Values on Case Temperature, per DIN EN 60747-5-2
Rev. 0 | Page 8 of 24
07540-005
0
ADuM5200/ADuM5201/ADuM5202
RECOMMENDED OPERATING CONDITIONS
Table 7.
Parameter OPERATING TEMPERATURE SUPPLY VOLTAGES 1 VDD1 @ VSEL = 0 V VDD1 @ VSEL = VDD1 V Minimum Load Minimum Power-On Slew Rate
1
Symbol TA VDD VDD IISO(MIN) VSLEW
Min -40 3.0 4.5 10 150
Max +105 3.6 5.5
Unit C V V mA V/ms
Each voltage is relative to its respective ground.
Rev. 0 | Page 9 of 24
ADuM5200/ADuM5201/ADuM5202 ABSOLUTE MAXIMUM RATINGS
Ambient temperature = 25C, unless otherwise noted. Table 8.
Parameter Storage Temperature (TST) Ambient Operating Temperature (TA) Supply Voltages (VDD, VISO)1 VISO Supply Current2 Input Voltage (VIA, VIB, VE1, VE2,RCSEL, VSEL)1, 3 Output Voltage (VOA, VOB)1, 3 Average Output Current per Data Output Pin4 Common-Mode Transients5
1 2
Table 9. Maximum Continuous Working Voltage Supporting a 50-Year Minimum Lifetime1
Parameter Max Unit
Rating -55C to +150C -40C to +105C -0.5 V to +7.0 V 100 mA -0.5 V to VDDI + 0.5 V -0.5 V to VDDO + 0.5 V -10 mA to +10 mA -100 kV/s to +100 kV/s
Reference Standard 50-year minimum lifetime Maximum approved working voltage per IEC 60950-1 Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10 Maximum approved working voltage per IEC 60950-1 Maximum approved working voltage per IEC 60950-1 and VDE V 0884-10
AC Voltage Bipolar Waveform Unipolar Waveform Basic Insulation
424
V peak
600
V peak
Reinforced Insulation
560
V peak
Each voltage is relative to its respective ground. The VISO provides current for dc and dynamic loads on the Side 2 input/output channels. This current must be included when determining the total VISO supply current. 3 VDDI and VDDO refer to the supply voltages on the input and output sides of a given channel, respectively. See the PCB Layout section. 4 See Figure 5 for maximum rated current values for various temperatures. 5 Refers to common-mode transients across the insulation barrier. Commonmode transients exceeding the absolute maximum ratings may cause latch-up or permanent damage.
DC Voltage Basic Insulation
600
V peak
Reinforced Insulation
560
V peak
1
Refers to continuous voltage magnitude imposed across the isolation barrier. See the Insulation Lifetime section for more details.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. 0 | Page 10 of 24
ADuM5200/ADuM5201/ADuM5202 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VDD1 1 GND1 2 VIA 3 VIB 4 RCIN 5 RCSEL 6 NC 7 GND1 8 NC = NO CONNECT
16 15
VISO GNDISO VOA
ADuM5200
14
13 VOB TOP VIEW (Not to Scale) 12 NC 11 10 9
VSEL GNDISO
07540-006
VE2
Figure 6. ADuM5200 Pin Configuration
Table 10. ADUM5200 Pin Function Descriptions
Pin No. Mnemonic 1 VDD1 2, 8 GND1 3 4 5 VIA VIB RCIN Description Primary Supply Voltage 3.0 V to 5.5 V. Ground 1. Ground reference for the isolator primary side. Pin 2 and Pin 8 are internally connected to each other, and it is recommended that both pins be connected to a common ground. Logic Input A. Logic Input B. Regulation Control Input. This pin must be connected to an RCOUT signal from another device or tied low. Note: This pin must not be tied high if RCSEL is low; this combination causes excessive voltage on the secondary side, damaging the ADuM5200 and possibly the devices that it powers. Control Input. Determines self-regulation (RCSEL high) mode or slave mode (RCSEL low) allowing external regulation. This pin is weakly pulled to the high state. In noisy environments, tie it either high or low. No Internal Connection. Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected to each other, and it is recommended that both pins be connected to a common ground. Data Enable Input. When high or no connect, the secondary outputs are active; when low, the outputs are in a high-Z state. Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V. In slave regulation mode, this pin has no function. Logic Output B. Logic Output A. Secondary Supply Voltage. Output for secondary side isolated data channels and external loads.
6 7, 12 9, 15 10 11 13 14 16
RCSEL NC GNDISO VE2 VSEL VOB VOA VISO
Rev. 0 | Page 11 of 24
ADuM5200/ADuM5201/ADuM5202
VDD1 1 GND1 2 VIA 3 VOB 4 RCIN 5 RCSEL 6 VE1 7 GND1 8 NC = NO CONNECT
16 15
VISO GNDISO VOA
ADuM5201
14
13 VIB TOP VIEW (Not to Scale) 12 NC 11 10 9
VSEL GNDISO
07540-007
VE2
Figure 7. ADuM5201 Pin Configuration
Table 11. ADuM5201 Pin Function Descriptions
Pin No. Mnemonic Description 1 VDD1 Primary Supply Voltage 3.0 V to 5.5 V. 2, 8 GND1 Ground 1. Ground reference for isolator primary side. Pin 2 and Pin 8 are internally connected to each other, and it is recommended that both pins be connected to a common ground. 3 VIA Logic Input A. 4 VOB Logic Output B. 5 RCIN Regulation Control Input. This pin must be connected to an RCOUT signal from another device or tied low. Note: This pin must not be tied high if RCSEL is low; this combination causes excessive voltage on the secondary side, damaging the ADuM5201 and possibly the devices that it powers. 6 RCSEL Control Input. Determines self-regulation mode (RCSEL high) or slave mode (RCSEL low) allowing external regulation. This pin is weakly pulled to the high state. In noisy environments, tie it either high or low. 7 VE1 Data Enable Input. When high or no connect, the primary output is active; when low, the outputs are in a high-Z state. 9, 15 GNDISO Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected to each other, and it is recommended that both pins be connected to a common ground. 10 VE2 Data Enable Input. When high or no connect, the secondary output is active; when low, the outputs are in a high-Z state. 11 VSEL Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V. In slave regulation mode, this pin has no function. 12 NC No Internal Connection. 13 VIB Logic Input B. 14 VOA Logic Output A. 16 VISO Secondary Supply Voltage. Output for secondary side isolated data channels and external loads.
Rev. 0 | Page 12 of 24
ADuM5200/ADuM5201/ADuM5202
VDD1 1 GND1 2 VOA 3 VOB 4 RCIN 5 RCSEL 6 VE1 7 GND1 8 NC = NO CONNECT
16 15
VISO GNDISO VIA
ADuM5202
14
13 VIB TOP VIEW (Not to Scale) 12 NC 11 10 9
VSEL GNDISO
07540-008
NC
Figure 8. ADuM5202 Pin Configuration
Table 12. ADuM5202 Pin Function Descriptions
Pin No. Mnemonic Description 1 VDD1 Primary Supply Voltage 3.0 V to 5.5 V. 2, 8 GND1 Ground 1. Ground reference for the isolator primary. Pin 2 and Pin 8 are internally connected to each other, and it is recommended that both pins be connected to a common ground. 3 VOA Logic Output A. 4 VOB Logic Output B. 5 RCIN Regulation Control Input. This pin must be connected to an RCOUT signal from another device or tied low. Note: This pin must not be tied high if RCSEL is low; this combination causes excessive voltage on the secondary side, damaging the ADuM5202 and possibly the devices that it powers. 6 RCSEL Control Input. Determines self-regulation (RCSEL high) mode or slave mode (RCSEL low) allowing external regulation. This pin is weakly pulled to the high state. In noisy environments, tie it either high or low. 7 VE1 Data Enable Input. When high or no connect, the primary output is active; when low, the outputs are in a high-Z state. 9, 15 GNDISO Ground Reference for Isolator Side 2. Pin 9 and Pin 15 are internally connected to each other, and it is recommended that both pins be connected to a common ground. 10, 12 NC No Internal Connection. 11 VSEL Output Voltage Selection. When VSEL = VISO, the VISO setpoint is 5.0 V. When VSEL = GNDISO, the VISO setpoint is 3.3 V. 13 VIB Logic Input B. 14 VIA Logic Input A. 16 VISO Secondary Supply Voltage. Output for secondary side isolated data channels and external loads.
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ADuM5200/ADuM5201/ADuM5202
Table 13. Truth Table (Positive Logic)
RCIN Input X X X X EXT-PWM 1 L X X H RCSEL Input H H H H L L X X L VSEL Input1 H L H L X L X X X VDDI Input 5.0 V 5.0 V 3.3 V 3.3 V X X X X X VISO Output 5.0 V 3.3 V 5.0 V 3.3 V X 0V X X X VIX Input X X X X X X H L X VOX Output X X X X X X H L X Operation Master mode operation, self-regulating. Power configuration not supported. Power configuration not supported. Master mode operation, self-regulating. Slave mode operation, regulation from another isoPower part. Low power mode, converter disabled. Data outputs valid for any active power configuration. Data outputs valid for any active power configuration. Note: This combination of RCIN and RCSEL is prohibited. Damage occurs on the secondary side of the converter due to excess output voltage at VISO. RCIN must be either low or a PWM signal from a master isoPower part.
1
PWM refers to the regulation control signal. This signal is derived from the secondary side regulator or from the RCIN input, depending on the value of RCSEL.
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ADuM5200/ADuM5201/ADuM5202 TYPICAL PERFORMANCE CHARACTERISTICS
40 35 30
3.5
IDD1 (A) AND POWER DISSIPATION (W)
3.0 2.5 POWER DISSIPATION
EFFICIENCY (%)
25 20 15 10 5 0 0 0.02 0.04 0.06 0.08 0.10 OUTPUT CURRENT (A)
07540-009
2.0
1.5 1.0 IDD
5V IN/5V OUT 3.3V IN/3.3V OUT
0.5
3.5
4.0 4.5 VDD1 (V)
5.0
5.5
6.0
Figure 9. Typical Power Supply Efficiency at 5 V/5 V and 3.3 V/3.3 V
1.0 0.9 0.8
POWER DISSIPATION (W)
Figure 12. Typical Short-Circuit Input Current and Power vs. VDD1 Supply Voltage
OUTPUT VOLTAGE (500mV/DIV)
0.7 0.6 0.5 0.4 0.3 0.2 0.1
07540-124
90% LOAD
5V IN/5V OUT 3.3V IN/3.3V OUT
DYNAMIC LOAD
10% LOAD (100s/DIV)
0 0 0.02 0.04 0.06 IISO (A) 0.08 0.10 0.12
Figure 10. Typical Total Power Dissipation vs. IISO with Data Channels Idle
0.12
Figure 13. Typical VISO Transient Load Response 5 V Output 10% to 90% Load Step
OUTPUT VOLTAGE (500mV/DIV)
0.10
OUTPUT CURRENT (A)
0.08
0.06
0.04
0 0 0.05 0.10 0.15 0.20 INPUT CURRENT (A) 0.25 0.30
07540-010
(100s/DIV)
Figure 11. Typical Isolated Output Supply Current, IISO as a Function of External Load, No Dynamic Current Draw at 5 V/5 V and 3.3 V/3.3 V
Figure 14. Typical Transient Load Response 3 V Output 10% to 90% Load Step
Rev. 0 | Page 15 of 24
07540-013
0.02
DYNAMIC LOAD
90% LOAD
5V IN/5V OUT 3.3V IN/3.3V OUT
10% LOAD
07540-012
07540-011
0 3.0
ADuM5200/ADuM5201/ADuM5202
25 BW = 20MHz 20
5V OUTPUT RIPPLE (mV)
20 5V IN/5V OUT 3.3V IN/3.3V OUT 16
CURRENT (mA)
07540-014
15
12
10
8
5
4
0
-5 0 0.5 1.0 1.5 2.0 TIME (s) 2.5 3.0 3.5
0 0 5 10 15 DATA RATE (Mbps) 20 25
4.0
Figure 15. Typical VISO = 5 V Output Voltage Ripple at 90% Load
16 BW = 20MHz 14
Figure 18. Typical ICH Supply Current per Reverse Data Channel (15 pF Output Load)
5
4
3.3V OUTPUT RIPPLE (mV)
5V 3.3V
12 10 8 6 4
1
07540-015
CURRENT (mA)
3
2
2 0 0 0.5 1.0 1.5 2.0 TIME (s) 2.5 3.0 3.5
0 0 5 10 15 DATA RATE (Mbps) 20 25
4.0
Figure 16. Typical VISO = 3.3 V Output Voltage Ripple at 90% Load
20 5V IN/5V OUT 3.3V IN/3.3V OUT 16
Figure 19. Typical IISO(D) Dynamic Supply Current per Input
3.0
2.5 5V 3.3V 2.0
CURRENT (mA)
12
CURRENT (mA)
1.5
8
1.0
4
0.5
07540-016
0 0 5 10 15 DATA RATE (Mbps) 20 25
0 0 5 15 10 DATA RATE (Mbps) 20 25
Figure 17. Typical ICH Supply Current per Forward Data Channel (15 pF Output Load)
Figure 20. Typical IISO(D) Dynamic Supply Current per Output (15 pF Output Load)
Rev. 0 | Page 16 of 24
07540-019
07540-018
07540-017
ADuM5200/ADuM5201/ADuM5202 TERMINOLOGY
IDD1(Q) IDD1(Q) is the minimum operating current drawn at the VDD1 pin when there is no external load at VISO and the I/O pins are operating below 2 Mbps, requiring no additional dynamic supply current. IDD1(Q) reflects the minimum current operating condition. IDD1(D) IDD1(D) is the typical input supply current with all channels simultaneously driven at a maximum data rate of 25 Mbps with the full capacitive load representing the maximum dynamic load conditions. Treat resistive loads on the outputs separately from the dynamic load. IDD1(MAX) IDD1(MAX) is the input current under full dynamic and VISO load conditions. tPHL Propagation Delay tPHL propagation delay is measured from the 50% level of the falling edge of the VIx signal to the 50% level of the falling edge of the VOx signal. tPLH Propagation Delay tPLH propagation delay is measured from the 50% level of the rising edge of the VIx signal to the 50% level of the rising edge of the VOx signal. Propagation Delay Skew (tPSK) tPSK is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. Channel-to-Channel Matching Channel-to-channel matching is the absolute value of the difference in propagation delays between the two channels when operated with identical loads. Minimum Pulse Width The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. Maximum Data Rate The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
Rev. 0 | Page 17 of 24
ADuM5200/ADuM5201/ADuM5202 APPLICATIONS INFORMATION
The dc-to-dc converter section of the ADuM520x works on principles that are common to most power supplies. It has a secondary side controller architecture with isolated pulse-width modulation (PWM) feedback. VDD1 power is supplied to an oscillating circuit that switches current into a chip scale air core transformer. Power transferred to the secondary side is rectified and regulated to either 3.3 V or 5 V. The secondary (VISO) side controller regulates the output by creating a PWM control signal that is sent to the primary (VDD1) side by a dedicated iCoupler data channel. The PWM modulates the oscillator circuit to control the power being sent to the secondary side. Feedback allows for significantly higher power and efficiency. The ADuM520x implements undervoltage lockout (UVLO) with hysteresis on the VDD1 power input. This feature ensures that the converter does not enter oscillation due to noisy input power or slow power on ramp rates. A minimum load current of 10 mA is recommended to ensure optimum load regulation. Smaller loads can generate excess noise on chip due to short or erratic PWM pulses. Excess noise generated this way can cause data corruption in some circumstances. The ADuM520x can accept an external regulation control signal (RCIN) that can be connected to other isoPower devices. This allows a single regulator to control multiple power modules without contention. When accepting control from a master power module, the VISO pins can be connected together adding their power. Because there is only one feedback control path, the supplies work together seamlessly. The ADuM520x can only regulate itself or accept regulation (slave device) from another device in this product line; it cannot provide a regulation signal to other devices. Note that the total lead length between the ends of the low ESR capacitor and the input power supply pin must not exceed 2 mm. Installing the bypass capacitor with traces more than 2 mm in length may result in data corruption. Consider bypassing between Pin 1 and Pin 8 and between Pin 9 and Pin 16 unless both of the common ground pins are connected together close to the package.
BYPASS < 2mm VDD1 GND1 VIA/VOA VIB/VOB RCIN RCSEL VE1/NC GND1 VISO GNDISO VOA/VIA VOB/VIB NC VSEL GNDISO
07540-020
VE2/NC
Figure 21. Recommended PCB Layout
In applications involving high common-mode transients, ensure that board coupling across the isolation barrier is minimized. Furthermore, design the board layout such that any coupling that does occur equally affects all pins on a given component side. Failure to ensure this can cause differential voltages between pins exceeding the absolute maximum ratings for the device (specified in Table 8) thereby leading to latch-up and/or permanent damage. The ADuM520x is a power device that dissipates approximately 1 W of power when fully loaded and running at maximum speed. Because it is not possible to apply a heat sink to an isolation device, the device primarily depends on heat dissipation into the PCB through the GND pins. If the device is used at high ambient temperatures, provide a thermal path from the GND pins to the PCB ground plane. The board layout in Figure 21 shows enlarged pads for Pin 2, Pin 8, Pin 9, and Pin 15. Multiple vias should be implemented from the pad to the ground plane to significantly reduce the temperature inside the chip. The dimensions of the expanded pads are at the discretion of the designer and depend on the available board space.
PCB LAYOUT
The ADuM520x digital isolators with 0.5 W isoPower integrated dc-to-dc converters require no external interface circuitry for the logic interfaces. Power supply bypassing is required at the input and output supply pins (see Figure 21). Note that low ESR bypass capacitors are required between Pin 1 and Pin 2 and between Pin 15 and Pin 16, as close to the chip pads as possible. The power supply section of the ADuM520x uses a 180 MHz oscillator frequency to efficiently pass power through its chip scale transformers. In addition, normal operation of the data section of the iCoupler introduces switching transients on the power supply pins. Bypass capacitors are required for several operating frequencies. Noise suppression requires a low inductance, high frequency capacitor, whereas ripple suppression and proper regulation require a large value capacitor. These are most conveniently connected between Pin 1 and Pin 2 for VDD1 and between Pin 15 and Pin 16 for VISO. To suppress noise and reduce ripple, a parallel combination of at least two capacitors is required. The recommended capacitor values are 0.1 F and 10 F for VDD1. The smaller capacitor must have a low ESR; for example, use of a ceramic capacitor is advised.
EMI CONSIDERATIONS
The dc-to-dc converter section of the ADuM520x components must operate at a very high frequency to allow efficient power transfer through the small transformers. This creates high frequency currents that can propagate in circuit board ground and power planes, causing edge emissions and dipole radiation between the primary and secondary ground planes. Grounded enclosures are recommended for applications that use these devices. If grounded enclosures are not possible, follow good RF design practices in layout of the PCB. See www.analog.com for the most current PCB layout recommendations specifically for the ADuM520x.
Rev. 0 | Page 18 of 24
ADuM5200/ADuM5201/ADuM5202
PROPAGATION DELAY PARAMETERS
Propagation delay is a parameter that describes the time it takes a logic signal to propagate through a component. The propagation delay to a logic low output may differ from the propagation delay to a logic high.
INPUT (VIX) 50%
50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated as shown in Figure 23.
100
MAXIMUM ALLOWABLE MAGNETIC FLUX DENSITY (kgauss)
10
tPLH
OUTPUT (VOX)
tPHL
50%
07540-118
1
0.1
Figure 22. Propagation Delay Parameters
Channel-to-channel matching refers to the maximum amount the propagation delay differs between channels within a single ADuM520x component. Propagation delay skew refers to the maximum amount the propagation delay differs between multiple ADuM520x components operating under the same conditions.
100k 10k 1M 10M MAGNETIC FIELD FREQUENCY (Hz)
100M
Figure 23. Maximum Allowable External Magnetic Flux Density
DC CORRECTNESS AND MAGNETIC FIELD IMMUNITY
Positive and negative logic transitions at the isolator input cause narrow (~1 ns) pulses to be sent to the decoder via the transformer. The decoder is bistable and is, therefore, either set or reset by the pulses, indicating input logic transitions. In the absence of logic transitions at the input for more than 1 s, a periodic set of refresh pulses indicative of the correct input state are sent to ensure dc correctness at the output. If the decoder receives no internal pulses of more than about 5 s, the input side is assumed to be unpowered or nonfunctional, in which case the isolator output is forced to a default state (see Table 13) by the watchdog timer circuit. The limitation on the magnetic field immunity of the ADuM520x is set by the condition in which induced voltage in the receiving coil of the transformer is sufficiently large to either falsely set or reset the decoder. The following analysis defines the conditions under which this may occur. The 3 V operating condition of the ADuM520x is examined because it represents the most susceptible mode of operation. The pulses at the transformer output have an amplitude greater than 1.0 V. The decoder has a sensing threshold at about 0.5 V, thus establishing a 0.5 V margin in which induced voltages can be tolerated. The voltage induced across the receiving coil is given by V = (-d/dt)rn2; n = 1, 2, ... , N where: is the magnetic flux density (gauss). N is the number of turns in the receiving coil. rn is the radius of the nth turn in the receiving coil (cm). Given the geometry of the receiving coil in the ADuM520x and an imposed requirement that the induced voltage be, at most,
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event occurs during a transmitted pulse (and is of the worst-case polarity), it reduces the received pulse from >1.0 V to 0.75 V--still well above the 0.5 V sensing threshold of the decoder. The preceding magnetic flux density values correspond to specific current magnitudes at given distances from the ADuM520x transformers. Figure 24 expresses these allowable current magnitudes as a function of frequency for selected distances. As shown, the ADuM520x is extremely immune and can be affected only by extremely large currents operated at high frequency very close to the component. For the 1 MHz example noted, a 0.5 kA current placed 5 mm away from the ADuM520x is required to affect the operation of the component.
1000
MAXIMUM ALLOWABLE CURRENT (kA)
DISTANCE = 1m 100
10 DISTANCE = 100mm 1 DISTANCE = 5mm 0.1
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 24. Maximum Allowable Current for Various Current-to-ADuM520x Spacings
Note that at combinations of strong magnetic field and high frequency, any loops formed by PCB traces can induce error
Rev. 0 | Page 19 of 24
07540-120
0.01
07540-119
Pulse width distortion is the maximum difference between these two propagation delay values and is an indication of how accurately timing of the input signal is preserved.
0.01
0.001 1k
ADuM5200/ADuM5201/ADuM5202
voltages sufficiently large enough to trigger the thresholds of succeeding circuitry. Exercise care in the layout of such traces to avoid this possibility. The preceding analysis assumes a 15 pF capacitive load on each data output. If the capacitive load is larger than 15 pF, the additional current must be included in the analysis of IDD1 and IISO(LOAD). To determine IDD1 in Equation 1, additional primary side dynamic output current (IAOD) is added directly to IDD1. Additional secondary side dynamic output current (IAOD) is added to IISO on a per channel basis. To determine IISO(LOAD) in Equation 2, additional secondary side output current (IAOD) is subtracted from IISO(MAX) on a per channel basis. For each output channel with CL greater than 15 pF, the additional capacitive supply current is given by IAOD = 0.5 x 10-3 x (CL - 15) x VISO) x (2f - fr) f > 0.5 fr (3) where: CL is the output load capacitance (pF). VISO is the output supply voltage (V). f is the input logic signal frequency (MHz); it is half of the input data rate expressed in units of Mbps. fr is the input channel refresh rate (Mbps).
07540-021
POWER CONSUMPTION
The VDD1 power supply input provides power to the iCoupler data channels as well as to the power converter. For this reason, the quiescent currents drawn by the data converter and the primary and secondary input/output channels cannot be determined separately. All of these quiescent power demands have been combined into the IDD1(Q) current shown in Figure 25. The total IDD1 supply current is the sum of the quiescent operating current, dynamic current IDD1(D) demanded by the I/O channels, and any external IISO load.
E IDD1(Q) IDD1(D) CONVERTER PRIMARY IDDP(D) PRIMARY DATA I/O 2-CHANNEL CONVERTER SECONDARY IISO(D) SECONDARY DATA I/O 2-CHANNEL IISO
Figure 25. Power Consumption Within the ADuM520x
CURRENT LIMIT AND THERMAL OVERLOAD PROTECTION
The ADuM520x is protected against damage due to excessive power dissipation by thermal overload protection circuits. Thermal overload protection limits the junction temperature to a maximum of 150C (typical). Under extreme conditions (that is, high ambient temperature and power dissipation), when the junction temperature starts to rise above 150C, the PWM is turned off, reducing the output current to zero. When the junction temperature drops below 130C (typical), the PWM turns on again, restoring the output current to its nominal value. Consider the case where a hard short from VISO to ground occurs. At first, the ADuM520x reaches its maximum current, which is proportional to the voltage applied at VDD1. Power dissipates on the primary side of the converter (see Figure 12). If self-heating of the junction becomes great enough to cause its temperature to rise above 150C, thermal shutdown activates, turning off the PWM and reducing the output current to zero. As the junction temperature cools and drops below 130C, the PWM turns on and power dissipates again on the primary side of the converter, causing the junction temperature to rise to 150C again. This thermal oscillation between 130C and 150C causes the part to cycle on and off as long as the short remains at the output. Thermal limit protections are intended to protect the device against accidental overload conditions. For reliable operation, externally limit device power dissipation to prevent junction temperatures from exceeding 130C.
Both dynamic input and output current is consumed only when operating at channel speeds higher than the rate of fr. Because each channel has a dynamic current determined by its data rate, Figure 17 shows the current for a channel in the forward direction, which means that the input is on the primary side of the part. Figure 18 shows the current for a channel in the reverse direction, which means that the input is on the secondary side of the part. Both figures assume a typical 15 pF load. The following relationship allows the total IDD1 current to be calculated: IDD1 = (IISO x VISO)/(E x VDD1) + ICHn; n = 1 to 4 (1) where : IDD1 is the total supply input current. ICHn is the current drawn by a single channel determined from Figure 17 or Figure 18, depending on channel direction. IISO is the current drawn by the secondary side external loads. E is the power supply efficiency at 100 mA load from Figure 9 at the VISO and VDD1 condition of interest. Calculate the maximum external load by subtracting the dynamic output load from the maximum allowable load. IISO(LOAD) = IISO(MAX) - IISO(D)n; n = 1 to 4 (2) where: IISO(LOAD) is the current available to supply an external secondary side load. IISO(MAX) is the maximum external secondary side load current available at VISO. IISO(D)n is the dynamic load current drawn from VISO by an input or output channel, as shown in Figure 17 and Figure 18. Data is presented assuming a typical 15 pF load
Rev. 0 | Page 20 of 24
ADuM5200/ADuM5201/ADuM5202
POWER CONSIDERATIONS
The ADuM5200/ADuM5201/ADuM5202 power input, data input channels on the primary side, and data input channels on the secondary side are all protected from premature operation by UVLO circuitry. Below the minimum operating voltage, the power converter holds its oscillator inactive and all input channel drivers and refresh circuits are idle. Outputs remain in a high impedance state to prevent transmission of undefined states during power-up and power-down operations. During application of power to VDD1, the primary side circuitry is held idle until the UVLO preset voltage is reached. At that time, the data channels initialize to their default low output state until they receive data pulses from the secondary side. When the primary side is above the UVLO threshold, the data input channels sample their inputs and begin sending encoded pulses to the inactive secondary output channels. The outputs on the primary side remain in their default low state because no data comes from the secondary side inputs until secondary power is established. The primary side oscillator also begins to operate, transferring power to the secondary power circuits. The secondary VISO voltage is below its UVLO limit at this point; the regulation control signal from the secondary is not being generated. The primary side power oscillator is allowed to free run in this circumstance, supplying the maximum amount of power to the secondary, until the secondary voltage rises to its regulation setpoint. This creates a large inrush current transient at VDD1. When the regulation point is reached, the regulation control circuit produces the regulation control signal that modulates the oscillator on the primary side. The VDD1 current is reduced and is then proportional to the load current. The inrush current is less than the short-circuit current shown in Figure 12. The duration of the inrush depends on the VISO loading conditions and the current available at the VDD1 pin. As the secondary side converter begins to accept power from the primary, the VISO voltage starts to rise. When the secondary side UVLO is reached, the secondary side outputs are initialized to their default low state until data is received from the corresponding primary side input. It can take up to 1 s after the secondary side is initialized for the state of the output to correlate with the primary side input. Secondary side inputs sample their state and transmit it to the primary side. Outputs are valid about 1 s after the secondary side becomes active. Because the rate of charge of the secondary side power supply is dependent on loading conditions, the input voltage, and the output voltage level selected, take care with the design to allow the converter sufficient time to stabilize before valid data is required. When power is removed from VDD1, the primary side converter and coupler shut down when the UVLO level is reached. The secondary side stops receiving power and starts to discharge. The outputs on the secondary side hold the last state that they received from the primary side. Either the UVLO level is reached and the outputs are placed in their high impedance state, or the outputs detect a lack of activity from the primary side inputs and the outputs are set to their default low value before the secondary power reaches UVLO.
THERMAL ANALYSIS
The ADuM520x consists of four internal die, attached to a split lead frame with two die attach paddles. For the purposes of thermal analysis, it is treated as a thermal unit with the highest junction temperature reflected in the JA from Table 3. The value of JA is based on measurements taken with the part mounted on a JEDEC standard 4-layer board with fine width traces and still air. Under normal operating conditions, the ADuM520x operates at full load across the full temperature range without derating the output current. However, following the recommendations in the PCB Layout section decreases the thermal resistance to the PCB allowing increased thermal margin at high ambient temperatures.
INCREASING AVAILABLE POWER
The ADuM520x devices are designed with the capability of running in combination with other compatible isoPower devices. The RCIN and RCSEL pins allow the ADuM520x to receive a PWM signal from another device through the RCIN pin and act as a slave to that control signal. The RCSEL pin chooses whether the part acts as a standalone self-regulated device or a slave device. When the ADuM520x is acting as a slave, its power is regulated by a PWM signal coming from a master device. This allows multiple isoPower parts to be combined in parallel while sharing the load equally. When the ADuM520x is configured as a standalone unit, it generates its own PWM feedback signal to regulate itself. The ADuM5000 can act as a master or a slave device, the ADuM5401, ADuM5402, ADuM5403, and ADuM5404 can only be master/standalone, and the ADuM520x can only be a slave/standalone device. This means that the ADuM5000, ADuM520x, and ADuM5401 to ADuM5404 can only be used in certain master/slave combinations as listed in Table 14. Table 14. Allowed Combinations of isoPower Parts
Slave Master ADuM5000 ADuM520x ADuM5401 to ADuM5404 ADuM5000 Yes No Yes ADuM520x Yes No Yes ADuM5401 to ADuM5404 No No No
The allowed combinations of master and slave configured parts listed in Table 14 is sufficient to make any combination of power and channel count. Table 15 illustrates how isoPower devices can provide many combinations of data channel count and multiples of the single unit power.
Rev. 0 | Page 21 of 24
ADuM5200/ADuM5201/ADuM5202
Table 15. Configurations for Power and Data Channels
Power Units 1-Unit Power 2-Unit Power 3-Unit Power 0 ADuM5000 master ADuM5000 master ADuM5000 slave ADuM5000 master ADuM5000 slave ADuM5000 slave Number of Data Channels 2 4 ADuM520x master ADuM5401 to ADuM5404 master ADuM5000 master ADuM520x slave ADuM5000 master ADuM5000 slave ADuM520x slave ADuM5401 to ADuM5404 master ADuM520x slave ADuM5401 to ADuM5404 master ADuM5000 slave ADuM5000 slave 6 ADuM5401 to ADuM5404 master ADuM121x ADuM5401 to ADuM5404 master ADuM520x slave ADuM5401 to ADuM5404 master ADuM520x slave ADuM5000 slave
INSULATION LIFETIME
All insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. The rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. In addition to the testing performed by the regulatory agencies, Analog Devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ADuM520x. Analog Devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. Acceleration factors for several operating conditions are determined. These factors allow calculation of the time to failure at the actual working voltage. The values shown in Table 9 summarize the peak voltage for 50 years of service life for a bipolar ac operating condition, and the maximum CSA/VDE approved working voltages. In many cases, the approved working voltage is higher than a 50-year service life voltage. Operation at these high working voltages can lead to shortened insulation life in some cases. The insulation lifetime of the ADuM520x depends on the voltage waveform type imposed across the isolation barrier. The iCoupler insulation structure degrades at different rates depending on whether the waveform is bipolar ac, unipolar ac, or dc. Figure 26, Figure 27, and Figure 28 illustrate these different isolation voltage waveforms. Bipolar ac voltage is the most stringent environment. The goal of a 50-year operating lifetime under the ac bipolar condition determines the maximum working voltage recommended by Analog Devices.
In the case of unipolar ac or dc voltage, the stress on the insulation is significantly lower. This allows operation at higher working voltages while still achieving a 50-year service life. The working voltages listed in Table 9 can be applied while maintaining the 50-year minimum lifetime, provided the voltage conforms to either the unipolar ac or dc voltage cases. Any cross insulation voltage waveform that does not conform to Figure 27 or Figure 28 should be treated as a bipolar ac waveform and its peak voltage limited to the 50-year lifetime voltage value listed in Table 9. The voltage presented in Figure 27 is shown as sinusoidal for illustration purposes only. It is meant to represent any voltage waveform varying between 0 V and some limiting value. The limiting value can be positive or negative, but the voltage cannot cross 0 V.
RATED PEAK VOLTAGE 0V
07540-121
Figure 26. Bipolar AC Waveform
RATED PEAK VOLTAGE
07540-122
0V
Figure 27. Unipolar AC Waveform
RATED PEAK VOLTAGE
07540-123
0V
Figure 28. DC Waveform
Rev. 0 | Page 22 of 24
ADuM5200/ADuM5201/ADuM5202 OUTLINE DIMENSIONS
10.50 (0.4134) 10.10 (0.3976)
16
9
7.60 (0.2992) 7.40 (0.2913)
1 8
10.65 (0.4193) 10.00 (0.3937)
1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122)
2.65 (0.1043) 2.35 (0.0925)
0.75 (0.0295) 0.25 (0.0098)
45
8 0 0.33 (0.0130) 0.20 (0.0079) 1.27 (0.0500) 0.40 (0.0157)
SEATING PLANE
COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 29. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model ADUM5200ARWZ 1, 2 ADuM5200CRWZ1, 2 ADuM5201ARWZ1, 2 ADuM5201CRWZ1, 2 ADuM5202ARWZ1, 2 ADuM5202CRWZ1, 2
1 2
Number of Inputs, VDD1 Side 2 2 1 1 0 0
Number of Inputs, VDD2 Side 0 0 1 1 2 2
Maximum Data Rate (Mbps) 1 25 1 25 1 25
Maximum Propagation Delay, 5 V (ns) 100 70 100 70 100 70
Maximum Pulse Width Distortion (ns) 40 3 40 3 40 3
Temperature Range -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C -40C to +105C
Package Description 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W
032707-B
Package Option RW-16 RW-16 RW-16 RW-16 RW-16 RW-16
Tape and reel are available. The additional -RL suffix designates a 13-inch (1,000 units) tape and reel option. Z = RoHS Compliant Part.
Rev. 0 | Page 23 of 24
ADuM5200/ADuM5201/ADuM5202 NOTES
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07540-0-10/08(0)
Rev. 0 | Page 24 of 24

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